- 01- Finalised RRAM-CMOS validation design package.
- 02- NTU Singapore, ITRI Taiwan on tape-out.
- 03- CIM with write-verify; BEOL on CMOS.
- 04- 22nm ultra-edge AI path.
dorsaVi (ASX: DVL) has finalised the design package for its first integrated resistive random access memory-complementary metal-oxide semiconductor (RRAM-CMOS) validation chip.
The company has developed the chip with NTU Singapore and ITRI Taiwan, and is now ready to move into tape-out and staged silicon implementation.
The design incorporates self-checking write-and-verify circuitry, compute-in-memory (CIM) capability and an integration pathway using standard commercial CMOS front-end wafers.
Results from the validation chip are expected to inform dorsaVi’s subsequent 22-nanometre implementation pathway for ultra-edge intelligence applications.
Ultra-Edge Roadmap
The validation chip is designed to prove three building blocks in dorsaVi’s ultra-edge intelligence roadmap, with its write-and-verify circuitry checking the programmed RRAM state after each write operation before data is accepted.
Its CIM macros allow the same RRAM array to store data and support local accumulation across up to 64 inputs.
RRAM stores data through resistance states rather than conventional charge storage.
Those resistance states can vary after write operations due to device variation, cycle effects, array parasitics and operating conditions.
The chip has also been designed so the RRAM layer can be integrated through back-end-of-line (BEOL) metal layers above the standard CMOS transistor circuitry.
Write-and-Verify Design
dorsaVi’s write-and-verify design is intended to reduce marginal memory states near the sensing threshold and improve the separation between stored zero and one states.
The resulting silicon data is expected to support future optimisation of write algorithms, sensing schemes, array yield, and long-term memory reliability.
Conventional computing architectures move data repeatedly between memory and a separate processor, increasing power use and latency in edge devices, whereas the CIM design reduces that movement by allowing selected compute operations to occur closer to where data is stored.
The architecture supports binary memory mode for standard storage and retrieval and CIM mode for using programmed resistance states as compute weights.
That approach could support faster local decision-making and lower energy consumption in future devices operating under tight power, latency or connectivity constraints.
TSMC-Sourced Wafers
The validation chip uses commercial CMOS front-end wafers sourced through Taiwan Semiconductor Manufacturing Company (TSMC).
Partner-led BEOL and RRAM integration steps are then designed to add the memory layer above the existing CMOS circuitry without changing the underlying transistor platform.
This pathway gives dorsaVi a route to evaluate manufacturability, node migration, and density scaling using established semiconductor foundry infrastructure.
The design targets future applications requiring low-power, non-volatile intelligence on device, including exoskeletons, defence, robotics, industrial AI, and intelligent sensing.
Manufacturable Architecture
Group chief executive officer Mathew Regan said finalising the design marked a significant milestone for the program.
“It confirms the architecture is manufacturable under standard commercial foundry conditions and clears the path to the physical silicon we need to validate performance.”
With the design complete, the program now moves from final design package into tape-out and staged silicon implementation.
“We are now focused on fabrication and on using the results to advance the program toward commercial scale,” Mr Regan added.
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