4DS Memory achieves better than expected megabit development success

Semiconductor development company 4DS Memory (ASX: 4DS) has achieved “significantly better than expected” analysis results from testing of its latest memory system offering known as the Fourth Platform Lot wafer.

4DS chief technology officer Ting Yen said the notable improvements to the 4Ds Platform Lot technology has been supported by the company’s ongoing collaboration with world-leading R&D and innovation hub in nanoelectronics and digital technologies developer, imec.

“We are very pleased with our imec collaboration and their comprehensive engineering support that made this significant achievement possible. We would like to thank imec for keeping a focused engineering and fab effort throughout the fabrication of this megabit array and completing on schedule,” Mr Yen said.

Notable upgrades identified

The latest examination of the Fourth Platform Lot has identified a number of notable upgrades over previous versions including successfully incorporating 4DS ReRAM memory cells into the imec megabit array.

Mr Yen said the company has also proven that 4DS Interface Switching ReRAM technology is transferable, while demonstrating a fully functional megabit array with 4DS Interface Switching ReRAM memory cells.

Notably, the tests also highlighted consistent read and write speeds equivalent to DRAM and proven endurance in excess of 2 billion cycles at DRAM read and write speed on a megabit array.

“These significant and robust results validate 4DS’ optimisation strategy and the decision to establish a duplicate of imec’s custom testing hardware and software for the megabit array at the 4DS Fremont facility,” Mr Yen said.

Further assessment planned

4DS’ interim executive chairman, David McAuliffe, described the megabit array results as a turning point for the company.

He added that the 4DS board will now consider the results in compiling its strategic planning over the coming months.

“Over the coming weeks additional analysis of the megabit array will continue and a meeting is being scheduled with imec in early October to discuss strategic plans.”

Optimisation changes identified

In late February of this year, 4DS revealed it had undertaken a number of optimisation changes which were incorporated into the schedule for manufacturing of the Fourth Platform Lot at imec.

The company also reported it had achieved cell operation in the megabit memory array of the Third Platform Lot utilising improved test capabilities, allowing the company to assess further exploration of optimised programming conditions with the access transistors and write circuitry of imec’s megabit memory platform.

The company believes these results showed that the 4DS Interface Switching ReRAM cells were more likely to be compatible with imec’s megabit memory platform, which de-risked the testing of the Fourth Platform Lot.

These new test results appear to have confirmed those assessments.

Future development options

With previous examination of the 4DS wafers confirming the successful programming of cells of the same size as present in the megabit memory array, the future focus will be on further optimising the etch process to ensure both residue-free etching and no crystalline damage to the 4DS PCMO layer.

Mr Yen said 4DS’ goal continues to be a focus on the uniqueness of its technology as an area-based ReRAM.

“imec’s megabit arrays have a lower limit of 60nm for a memory cell but 4DS testing has demonstrated that our ReRAM scales consistently across available cell geometries on megabit arrays,” he said.

“The read/write speed and endurance parameters are critical to the Company’s goals in the memory space requiring DRAM-like performance characteristics. 4DS’ ReRAM performance profile to suitably meet this goal has been clearly demonstrated on the Fourth Platform Lot.”